The continuing popularity of portable electronic devices presents manufacturers with significant challenges. Increasing capability of electronic devices is moderated by considerations of cost, size, weight, and battery life. These considerations have increasingly resulted in higher levels of semiconductor integration. Thus, portable electronic devices frequently embed volatile and nonvolatile memory, control, signal processors, and other circuit functions on a single integrated circuit. Further optimization of these portable electronic devices dictates even greater reduction in geometric feature sizes and spaces between these geometric features. Shrinking feature sizes require lower supply voltages to limit maximum electric fields. Even with lower supply voltages, however, special considerations are required for reliable device operation.
Referring to FIG. 1, there is an electrically erasable programmable read only memory (EEPROM) cell of the prior art. The EEPROM memory cell is preferably formed on a P-type substrate 122 between field oxide isolation regions 120. These field oxide isolation regions 120 are preferably formed by local oxidation of silicon (LOCOS) as is well known to those having ordinary skill in the art. The EEPROM memory cell includes N+ source 108 and drain 116 regions. Lightly doped drain (LDD) regions 109 are formed adjacent the N+ source 108 and drain 116 regions. An N+ tunnel implant region 114 is formed adjacent and in electrical contact with the N+ drain region 116. A gate oxide region 110 is formed over the source 108, drain 116, and tunnel implant region 116. The gate oxide region 110 is etched to form a thin tunnel oxide region 112. A first polycrystalline silicon floating gate 106 is formed over an active area between field oxide isolation regions 120. A control gate dielectric region is formed over the first polycrystalline silicon floating gate 106. A second polycrystalline silicon control gate 104 is formed over the control gate dielectric region. A sidewall dielectric 107 of preferably silicon nitride is formed adjacent the first polycrystalline silicon floating gate and the second polycrystalline silicon control gate 104. A conductive layer of preferably titanium silicide (not shown) is formed at the upper surface of the N+ source 108 and drain 116 regions and the polycrystalline silicon control gate 104. A dielectric region 118 is formed over the EEPROM memory cell. Contact holes are etched in the dielectric 118, and metal electrodes 100 and 102 are formed to provide electrical contact to respective source and drain terminals of the EEPROM memory cell.
In operation, the floating gate 106 stores a charge indicative of a logical one or zero. By convention, when the EEPROM cell is programmed to a logical one state, it stores a negative charge on floating gate 106. Alternatively, when the EEPROM cell is erased to a logical zero state, negative charge is removed from the floating gate 106. Both program and erase operations preferably transfer charge to and from the floating gate 106 by Fowler-Nordheim tunneling. During an erase operation, for example, a high voltage is applied to drain terminal 102, control gate 104 is connected to ground, and source terminal 100 floats in a high impedance state. The high positive voltage at terminal 102 is applied to N+ drain region 116 and N+ tunnel implant region 114. This high voltage produces a high electric field across the thin tunnel oxide 112 window, thereby imparting sufficient energy to permit negative charge to tunnel from floating gate 106 and through tunnel oxide window 112 to N+ tunnel implant region 114.
The thickness of tunnel window oxide 112, therefore, is critical to proper operation of the EEPROM memory cell in both program and erase modes. If tunnel window oxide 112 is too thin, long-term data retention may be degraded by excessive leakage. Alternatively, if tunnel window oxide 112 is too thick, insufficient charge may be removed during erase to produce a zero. Manufacturing the correct tunnel window oxide 112 thickness is greatly complicated by the presence of N+ tunnel implant region 114. N+ tunnel implant region 114 must have a sufficiently high surface concentration to prevent inversion at the interface with tunnel window oxide 112. This high concentration of N+ tunnel implant region 114, however, greatly enhances oxide growth. For example, a gate oxide recipe that produces 285 Å of gate oxide on a lightly doped P-type silicon wafer will result in a gate oxide thickness of about 325 Å if 2E14 atoms/cm2 of N+ arsenic (As) is implanted at an energy of 80 KeV prior to gate oxidation. Gate oxide 10 is then etched from the tunnel window region 112. The tunnel oxide 112 is then regrown to a target thickness of 70 Å. Relatively small variations of the N+ region 114 implant dose, however, can produce large variations of 70 Å to 150 Å tunnel oxide 112 thickness. Thus, a method to reduce this critical variation of tunnel oxide 112 thickness in manufacturing and the corresponding variation of EEPROM memory cell program and erase operation is needed.